VSD - Library characterization and modelling - Part 1

VSD - Library characterization and modelling - Part 1

If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word 'Library'. This course explains you, in detail, what it exactly means. 

You can call Library as the soul and heart of Semiconductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are incomplete. 

Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes. 

Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.

This course is designed in collaboration with leading characterization company Paripath, who have designed the state-of-the-art characterization software called GUNA

I would like to Thank complete Paripath team for helping me in designing experiments for this course. This course is motivated by desire to fill gap on characterization and modelling

Trademark:

Liberty is a registered trademark of Synopsys Inc.

Verilog is a registered trademark of Cadence Design Systems, Inc.

SDF and SPEF are trademarks of Open Verilog International

Get in right now and have an unforgettable journey of your life...

Happy Learning!!

VLSI - The heart of STA, PNR, CTS and Crosstalk

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What you will learn

• Understand timing, noise and power libraries syntax and semantics
• Develop models for logic gates and macros
• Use the above generated models and do STA

Rating: 3.6

Level: Expert Level

Duration: 5 hours

Instructor: Kunal Ghosh