VSD - Embedded-UVM

VSD - Embedded-UVM

Of course, there is a requirement for open-source verification, but that’s not the only thing we want to cater to. There are other verification trends and challenges which system Verilog and other verification platforms are not able to meet. So, we want to position Embedded-UVM for that. In the past decade or so, the major thing which is making verification tougher than it used to be, is the death of Moore’s law.

As far as processor frequency goes, it stabilizes at 4GHz and it's coming down as we move to multi-core processors. So, when you look at it from a simulation perspective, post-2005 it is becoming increasingly difficult to run simulations on bigger chips.

Chip size keeps increasing, while processor speed is stagnant and hence, simulation is a limiting factor. Simulation speed is going to be limited unless we move to multi-core processors. Contemporary EDA tools run RTL simulations in a multi-core environment. System Verilog doesn’t run in a multi-core environment.

Therefore, test-bench runs on one thread and RTL runs on multiple threads. RTL is more formal in nature, in sense, it can be synthesized, it can be partitioned, different partitions can run on different processors, while test-bench is behavioral in nature and it cannot be partitioned the way RTL can be.

About Speaker:

Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch.

For the past 8 years, he has been working for Coverity Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.

Opensource Verification and Emulation

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What you will learn

• We take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC FPGA based Emulation
• We learn how to code Embedded UVM powered testbench for a hardware accelerator design IP
• The test bench is then adapted to Cyclone V and Ultrascale Zynq based platforms to demonstrate Embedded UVM powered low-cost SoCFPGA based emulation solutions.

Rating: 3.8

Level: Intermediate Level

Duration: 4 hours

Instructor: Kunal Ghosh