Partial Reconfiguration with FPGA

Partial Reconfiguration with FPGA

This course covers the basics of "Partial Reconfiguration (PR)" flow with Xilinx VIVADO tool and FPGA. We have followed the standard syllabus on this training, so the enthusiast who want to learn will get in depth knowledge and skills on the "Partial Reconfiguration". PR flow is necessary when there is larger design and need to fit on the specific series of FPGA. PR flow is followed on the Xilinx as well as Intel-Altera based design tools and FPGA.

This are the major points which covered on this course:

1. Partial Reconfiguration flow with Xilinx VIVADO and FPGA [7 series, Ultrascale and Ultrascale+ FPGAs]

2. Using Debugging method [using ILA and VIO] on Partial Reconfiguration flow

3. Designing PR flow with Partial Reconfigurable Controller

4. PR flow with MicroBlaze

5. BitStream Relocation-overview

Learn about the complete Partial Reconfiguration Flow with Xilinx VIVADO and FPGA

Url: View Details

What you will learn

• Partial Reconfiguration Design Flow
• Xilinx VIVADO tool and FPGA devices for Partial Reconfiguration Flow
• Debugging the PR Design with ILA and VIO

Rating: 3.15

Level: Expert Level

Duration: 2 hours

Instructor: Digitronix Nepal