Fundamentals of Verification and System Verilog

Fundamentals of Verification and System Verilog

This course is introduced for learners who wants to learn fundamental concepts of Verification and basic concepts of SystemVerilog. It is assumed that learner is aware of the Verilog hardware description language. In this course, learners will be introduced to why verification is to be done and what is verification. One of the verification language SystemVerilog constructs will be introduced.  Layered testbench and its various components will be discussed. Learner's will also be introduced to various data types, procedural control statements and interfaces in SystemVerilog. Course is being taught with various examples and learner can monitor self-progress by attempting quiz and assignment in each section.

Simple course for students and engineers who wants to learn concepts of verification and basic SystemVerilog Constructs

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What you will learn

• Significance of verification
• Verification options, methodologies, approaches and plan
• Examples to practice on verification tool EDA Playground

Rating: 4.3

Level: Beginner Level

Duration: 21.5 hours

Instructor: Surendra Rathod