Circuit Design for High Speed Serial Links

Circuit Design for High Speed Serial Links

NOTE: New content added on Equalizer - CTLE

In high-speed communication applications , a large amount of data may have to be communicated from one chip to another. Unfortunately, the number of input and output (I/O) pins is limited on a System-on-Chip (SoC). Serializing and deserializing (also called "SerDes") the data using a serial link between the chips at a high speed is the way to achieve high speed data transfers. The data transfers can happen in short and long distances. The architecture of the design depends not only on the distance, but also on the speed of transfer (frequency of operation). Serial communication is used in machine to machine (M2M) and chip-to-chip (C2C) communications greatly. In fact, each smart phone in our hands has multiple such SerDes in it. In this course we will discuss the overview and the challenges of designing high speed SerDes.

This course is specially curated and designed for freshers from the undergraduate and post graduate degrees. This course can act a refresher to experienced analog IC design engineers and high speed design engineers too.  The topics you will address in this course are:

1. Need for High Speed Serial Links / SERDES

2. Architecture of SERDES - How to choose the architecture

3. Impact of the Channel and its dependence of data rates

4. Need for Signal Equalization and how it is solved.

5. CTLE Continuous Time Linear Equalization

6. A quick overview of the Major blocks of high speed serial links.

7. Clocking using PLL and DLL

Design circuits for Gigabits of data transfer

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What you will learn

• High Speed Serial Links Overview
• Benefits of high speed links
• How to decide the Receiver Architecture Design

Rating: 3.1

Level: All Levels

Duration: 3 hours

Instructor: Dr G S Javed